Field of the Invention
The present invention relates to error checking and correcting of input/output data of a semiconductor memory device, and in particular to error checking, correcting and programming of input/output data of a NAND-type flash memory.
Description of the Related Art
Semiconductor memories, like flash memories, DRAMs, etc., have been increasing their integration level year after year, so it has become difficult to manufacture a memory element without defects. Therefore, a redundant scheme is utilized on the memory chip to compensate for physical defects of a memory element generated during the manufacturing process. For example, in a redundant scheme, a redundant memory is arranged to compensate for the memory elements with physical defects. In addition to physical compensation by a redundant memory, an ECC (Error Checking and Correcting) circuit is utilized on the semiconductor memory as a strategy for handling soft errors.
In a NAND-type flash memory, data is repeatedly programmed or erased, so the charge-holding characteristics become worse due to the deterioration of the tunnel insulation layer, or the threshold voltage is changed due to the charges trapped in the tunnel insulation layer. Those situations may cause bit errors. In Patent document 1, an ECC circuit is utilized as a strategy for handling those bit errors. Especially in the case of the memory cells which are near a block selection transistor, which have a tendency toward high bit error rates because of the variation of patterns formed by lithography or the variation of ion injection at the time the diffusion layer is formed. Thus, those memory cells store ECC codes to compensate for these kinds of bit errors as much as possible.
NAND-type flash memories include a species where a memory cell stores 1-bit data and a species where a memory cell stores multi-bit data. In Patent document 2, an error correction scheme for multi-bit data is disclosed. Patent document 3 further discloses a flash memory which attaches ECC parity to the input date to generate an ECC symbol, writes the generated ECC symbol into the physical block, corrects errors by the ECC symbol when there are errors in the page data read out from the physical block, treats the physical block of which the number of corrected errors is greater than a threshold value as a warning block, registers this physical block in a table, and lowers the priority of the warning block when data is written.
Patent document 1: Patent publication no. JP 2010-152989
Patent document 2: Patent publication no. JP 2008-165805
Patent document 3: Patent publication no. JP 2010-79486
FIG. 1 shows an example of a programming operation of a NAND-type flash memory which has a conventional ECC circuit integrated on the chip. The programming data input from the external input/output terminal is loaded into a page buffer/sense circuit 400. When the loading is finished, a transfer circuit 410 transfers the programming data held by the page buffer/sense circuit 400 to an ECC circuit 420. The transfer circuit 410 includes, for example, a plurality of transfer transistors capable of transferring data bi-directionally. Each transistor is driven by a control signal TC which is commonly supplied to each gate. The ECC circuit 420 performs an ECC calculation for the received data and generates error-correction symbols (error codes). The generated error-correction symbols are written back to a predetermined domain of the page buffer/sense circuit 400 by the ECC circuit 420. Then the page buffer/sense circuit 400 programs the input programming data and the error-correction symbols into a selected page in the memory array.
However, the transfer time of data from the page buffer/sense circuit 400 to the ECC circuit 420 may be relatively long. If the page buffer/sense circuit 400 uses “sector” as a unit of receiving data and the ECC circuit 420 performs an ECC calculation for the data in sector units, the programming data cannot be programmed until the transfer of all sectors of the page buffer/sense circuit 400 is finished. Furthermore, if the number of bits in a page increases due to high integration, the data transfer time and the time required for the calculation of the ECC circuit also increase proportionally. Therefore, the time required for programming the programming data into the memory array becomes longer.
To solve the above problems, the invention provides a semiconductor memory device capable of maintaining the reliability of data and accelerating the programming operation.